1. Field of the Invention
The disclosed invention relates to analog-digital converters, in particular to SAR converters (SAR: Successive Approximation Register). Furthermore, the disclosed invention relates to SAR converter topologies which provide redundancy by using 1.5 bit conversion steps.
2. Description of the Related Art
SAR converters for analog-digital conversion are well known in the art. In particular, SAR converters are frequently used in integrated CMOS devices since they provide a reasonable resolution and conversion time and can be implemented by optimally utilizing the advantages of the CMOS technology, which are small-sized CMOS-switches and capacitors having well-defined relative capacitance.
SAR converters generally include at least one capacitor bank with capacitors of different values, usually with a relation between their capacitance values by a factor of 2n (n: integer). Each capacitor is connected between the signal line and a ground potential and is further associated with a switch so that the capacitor can be disconnected from the ground potential and connected to a reference voltage. In a sampling phase, a voltage level of an input signal applied on the signal line is stored on each capacitor of the capacitor bank. In a following second phase, a reference voltage is applied successively to ground plates of the capacitors and the resulting voltage on the signal line is compared with the reference voltage level. After a connection of the ground plate of a capacitor with the reference voltage is made, the result bit of the comparison is stored in a register. Furthermore, the result bit determines the final state of the switch previously set so that a further switching of the previously set switch may be carried out after the result bit of the single comparison has been determined. In other words, the result bits represent the switching states for the most significant capacitors, i.e. the capacitors having the highest capacities. Depending on the result bit of each single comparison step it is decided whether to keep the recently switched capacitor in the last switching position or to return connecting its ground plate with the ground potential again.
Beginning with the most significant bit associated with the capacitor with the highest capacitance, the input signal is sampled by subsequently applying the reference potential to the ground plates of the respective capacitors, followed by a comparison the result of which firstly is stored. Secondly, the result determines whether the ground plate of the capacitor is kept connected with the reference voltage or returned to ground potential. When all of the capacitors have been sampled this way, the stored result bits correspond to a digital representation of a sampled voltage of the input signal.
For conventional SAR converters, the capacitor ladder comprises capacitances of values C, C, 2C, 4C, 8C, . . . , 2n C. This kind of binary ladder can be used to obtain a binary result in the register which directly corresponds to the sampled voltage of the input signal as a binary digital value.
Although the above description of a SAR converter relates to a non-differential input signal, the same concept can be applied to differential input signals, wherein two capacitor ladders are connected with the inverting and non-inverting input of the comparator. For each comparison step the potential of both signal lines is shifted simultaneously, and the result of the comparison is stored as a result bit in the respective register.
SAR converters can be provided with redundancy. Redundancy is achieved such that the value range defined by the result bit of the previously performed comparison step is extended for a next comparison so that a conversion result can finally be obtained that is outside the value range defined by one or more of the result bits. Such redundancy can increase the reliability of the ADC considerably because small conversion errors for input values that fall close to a decision threshold of one conversion cycle can be corrected in consecutive conversion steps. Usually, in a converter with a specific resolution the provision of redundancy increases the number of cycles (comparison steps) necessary to perform the full conversion. Thus, increasing the redundancy means increasing the overall conversion time.
Furthermore, the range decision can be altered from a binary to a ternary or even a higher degree (e.g. quaternary) of decisions by parallelizing the comparison steps. In case of a ternary analog-digital conversion, two conversion paths are simultaneously applied, defining a lower and the upper decision threshold level for each single conversion to obtain a trisection of the respective discrimination range. Combining redundancy with a higher degree of decisions (binary, ternary, quaternary etc.) can provide a decent trade-off between a number of overall conversion cycles and the achieved degree of redundancy.
Apart from the number of conversion cycles necessary to perform the full analog-digital conversion result, the reduction of the cycle time for each comparison step is essential in order to keep the overall conversion time low. In case redundancy is obtained by using a higher than binary degree of conversion, the conversion cycle time is substantially increased since the comparison results have to be mapped to a switching scheme for the switches which are associated with the capacitors using a mapping logic. This mapping logic is required to calculate the capacitance values for each individual conversion cycle in a way to achieve a specific redundancy level for this cycle. The signal processing using this mapping logic consumes time in each conversion cycle, so that the overall conversion time is increased by the product of the signal propagation time in the mapping logic and the number of conversion cycles.